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1 low dropout voltage (0.6v at 0.5a) 3% output accuracy active external delay for reset protection circuitry reverse battery protection +60v, -50v peak transient voltage short circuit protection internal thermal overload protection reset reset features package options 5 l to-220 7 l d 2 pak tab (gnd) tab (gnd) 1 cs8126, -1, -2 5v, 750ma low dropout linear regulator with delayed reset cs8126,-1,-2 description the cs8126 is a low dropout, high cur- rent 5v linear regulator. it is an improved replacement for the cs8156. improvements include higher accuracy, tighter saturation control, better supply rejection, and enhanced circuit- ry. familiar pnp regulator features such as reverse battery protection, over- voltage shutdown, thermal shutdown, and current limit make the cs8126 suit- able for use in automotive and battery operated equipment. additional on- chip filtering has been included to enhance rejection of high frequency transients on all external leads. an active microprocessor func- tion is included on-chip with externally programmable delay time. during power-up, or after detection of any error in the regulated output, the lead will remain in the low state for the duration of the delay. types of errors include short circuit, low input voltage, overvoltage shut- down, thermal shutdown, or others that cause the output to become unregulat- ed. this function is independent of the input voltage and will function correct- ly with an output voltage as low as 1v. hysteresis is included in both the reset and delay comparators for enhanced noise immunity. a latching discharge circuit is used to discharge the delay capacitor, even when triggered by a rel- atively short fault condition. this circuit improves upon the commonly used scr structure by providing full capaci- tor discharge (0.2v type). note:the cs8126 is lead compatible with the lm2925, tle4260, l4947, lm2927, and lm2926. reset reset reset block diagram v out v in over voltage shutdown pre- regulator regulated supply for circuit bias bandgap reference thermal shutdown error amp anti-saturation and current limit charge current generator latching discharge reset comparator delay comparator - + + - q r s v discharge + - + - delay gnd reset cs8126-1 1v in 2v out 3 gnd 4 delay 5 reset cs8126-2 1v in 2 reset 3 gnd 4 delay 5v out 16 lead soic wide 1 v in v out delay reset v out(sense) nc nc gnd nc nc nc nc nc nc nc nc rev. 5/4/99 1 1v in 2v out 3v out(sense) 4 gnd 5 delay 6 reset 7nc on semiconductor 2000 south county trail, east greenwich, ri 02818 tel: (401)885?3600 fax: (401)885?5786 n. american technical support: 800-282-9855 web site: www.cherry?semi.com
2 parameter test conditions min typ max unit electrical characteristics: t a = -40? to +125?, t j = -40? to +150?, v in = 6 to 26v, i o = 5 to 500ma, r reset = 4.7k ? to v cc, unless otherwise noted. absolute maximum ratings power dissipation.............................................................................................................. ...............................internally limited peak transient voltage (46v load dump) ........................................................................................ .........................-50v, 60v output current ................................................................................................................. ................................internally limited esd susceptibility (human body model)........................................................................................... ...................................4kv junction temperature ........................................................................................................... ..................................-40c to 150c storage temperature............................................................................................................ ...................................-55c to 150c lead temperature soldering wave solder (through hole styles only) ..........................................10 sec. max, 260c peak reflow (smd styles only) ..........................................60 sec. max above 183c, 230c peak output stage (v out ) output voltage 4.85 5.00 5.15 v dropout voltage i out = 500ma 0.35 0.60 v supply current i out 10ma 2 7 ma i out 100ma 6 12 i out 500ma 55 100 line regulation v in = 6 to 26v, i out = 50ma 5 50 mv load regulation i out = 50 to 500ma, v in = 14v 10 50 mv ripple rejection f = 120hz, v in = 7 to 17v, 54 75 db i out = 250ma current limit 0.75 1.20 a overvoltage shutdown 32 40 v maximum line transient v out 5.5v 95 v reverse polarity input v out -0.6v, 10 ? load -15 -30 v voltage dc reverse polarity input 1% duty cycle, t < 100ms, -80 v voltage transient 10 ? load thermal shutdown guaranteed by design 150 180 210 c and delay functions delay charge current v delay = 2v 5 10 15 a threshold v out increasing, v rt(on) 4.65 4.90 v out - 0.01 v v out decreasing, v rt(off) 4.50 4.70 v out - 0.15 v hysteresis v rh = v rt(on) - v rt(off) 150 200 250 mv delay threshold charge, v dc(hi) 3.25 3.50 3.75 v discharge, v dc(lo) 2.85 3.10 3.35 v delay hysteresis 200 400 800 mv output voltage low 1v < v out < v rtl , 3k ? to v out 0.1 0.4 v output leakage v out > v rt(on) 010a current delay capacitor discharge latched ?on?, 0.2 0.5 v discharge voltage v out > v rt delay time c delay = 0.1f* (note 1) 16 32 48 ms delay time = = c delay x 3.2 x 10 5 (typ) note 1: assumes ideal capacitor c delay v delay threshold charge i charge reset reset reset reset reset cs8126, -1, -2
3 typical performance characteristics 0.0 0.0 icq (ma) v in (v) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 r load = 25 ? 125?c 25?c -40?c 0.0 0.0 icq (ma) v in (v) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 room temp. 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100.0 110.0 120.0 r load = 6.67 r load = 10 r load = 25 r load = no load 0.0 0.0 v out (v) v in (v) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 r load = 25 ? 125?c 25?c -40?c v out vs v in over temperature i cq vs. v in over r load i cq vs. v in over temperature 0.0 0.0 v out (v) v in (v) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 room temp. rload = no load rload = 6.67 rload = 10 v out vs. v in over r load package lead description package lead # lead symbol function cs8126, -1, -2 5 lead to-220 7lead 16 lead cs8126-1 cs8126-2 d 2 pak soic wide 111 1v in unregulated supply voltage to ic. 252 16v out regulated 5v output. 3 3 4 11 gnd ground connection. 4 4 5 8 delay timing capacitor for function. 5 2 6 6 cmos/ttl compatible output lead. goes low after detection of any error in the regulated output or during power up. 314v out(sense) remote sensing of output voltage. 7 2, 3, 4, 5, 7, 9, nc no connection. 10, 12, 13, 15 reset reset reset
4 0 0 dropout voltage (mv) output current (ma) 100 200 300 400 500 600 700 800 100 200 300 400 500 600 700 800 900 25?c -40?c 125?c 0 0 quiescent current (ma) output current (ma) 10 20 30 40 50 60 70 80 90 100 100 200 300 400 500 600 700 800 v in = 14v 125?c 25?c -40?c 0 10 0 rejection (db) freq. (hz) 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 20 30 40 50 60 70 80 90 i out = 250ma c out = 10 f, esr = 10 ? c out = 10 f, esr = 1 ? c out = 10 f, esr = 1 & 0.1 f, esr = 0 ripple rejection quiescent current vs. output current over temperature dropout voltage vs. output current over temperature typical performance characteristics: continued -100 0 line regulation (mv) output current (ma) -80 -60 -40 -20 0 20 40 60 80 100 100 200 300 400 500 600 700 800 v in 6-26v temp = 25?c temp = 40?c temp = 125?c -14 0 load regulation (mv) output current (ma) -12 -10 -8 -6 -4 -2 0 2 4 6 100 200 300 400 500 600 700 800 temp = 25?c temp = 125?c v in = 14v temp = -40?c load regulation vs. output current over temperature line regulation vs. output current over temperature 10 0 esr (ohms) output current (ma) 10 1 10 2 10 3 10 1 10 2 10 3 10 -4 10 0 10 -1 10 -2 10 -3 c out = 68 f c out = 47 f c out = 47/68 f stable region output capacitor esr cs8126, -1, -2
5 the cs8126 function, has hysteresis on both the reset and delay comparators, a latching delay capacitor discharge circuit, and operates down to 1v. the circuit output is an open collector type with on and off parameters as specified. the output npn transistor is controlled by the two circuits described (see block diagram). low voltage inhibit circuit this circuit monitors output voltage, and when the output voltage falls below v rt(off) , causes the output tran- sistor to be in the on (saturation) state. when the output voltage rises above v rt(on) , this circuit permits the output transistor to go into the off state if allowed by the delay circuit. reset delay circuit this circuit provides a programmable (by external capaci- tor) delay on the output lead. the delay lead pro- vides source current to the external delay capacitor only when the "low voltage inhibit" circuit indicates that out- put voltage is above v rt(on) . otherwise, the delay lead sinks current to ground (used to discharge the delay capacitor). the discharge current is latched on when the output voltage falls below v rt(off) . the delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. this feature ensures a controlled pulse is generated following detection of an error condition. the circuit allows the output transistor to go to the off (open) state only when the voltage on the delay lead is higher than v dc(h1) . the delay time for the function is calculated from the formula: delay time = delay time = c delay 3.2 10 5 if c delay = 0.1f, delay time (ms) = 32ms 50%: i.e. 16ms to 48ms. the tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. c delay v delay threshold i charge reset reset reset reset reset reset reset reset reset reset reset circuit waveform v rh v out v rt(on) v rt(off) v rl delay v dc(hi) v dc(lo) v dh t delay v dis (3) (1) (2) (2) reset (1) = no delay capacitor (2) = with delay capacitor (3) = max: reset voltage (1.0v) circuit description cs8126, -1, -2
6 application diagram application notes c 1 * 100nf v in delay gnd reset v out cs8126 c 2 ** 10 f to 100 f r rst 4.7k ? delay 0.1 f the output or compensation capacitor helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr, can cause insta- bility. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low tem- peratures (-25c to -40c), both the value and esr of the capacitor will vary considerably. the capacitor manufac- turers data sheet usually provides this information. the value for the output capacitor c 2 shown in the test and applications circuit should work for most applica- tions, however it is not necessarily the optimized solution. to determine an acceptable value for c 2 for a particular application, start with a tantalum capacitor of the recom- mended value and work towards a less expensive alterna- tive part. step 1: place the completed circuit with a tantalum capac- itor of the recommended value in an environmental cham- ber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscil- lations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4 : maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage condi- tions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capaci- tor will usually cost less and occupy less board space. if the output oscillates within the range of expected operat- ing conditions, repeat steps 3 and 4 with the next larger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: remove the unit from the environmental chamber and heat the ic with a heat gun. vary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regula- tor performance. most good quality aluminum electrolytic capacitors have a tolerance of +/- 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. the maximum power dissipation for a single output regu- lator (figure 1) is: p d(max) = {v in(max) - v out(min) }i out(max) + v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the applica- tion, and i q is the quiescent current the regulator consumes at i out(max) . stability considerations calculating power dissipation in a single output linear regulator c 1 * is required if the regulator is far from the power source filter. c 2 ** is required for stability cs8126, -1, -2
7 application notes: continued once the value of p d(max) is known, the maximum permis- sible value of r ja can be calculated: r ja = (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja 's less than the calculated value in equation 2 will keep the die temperature below 150c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja . r ja = r jc + r cs + r sa (3) where: r jc = the junction?to?case thermal resistance, r cs = the case?to?heatsink thermal resistance, and r sa = the heatsink?to?ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers. 150c - t a p d heat sinks v in smart regulator v out i out i in i q control features } figure 1. single output regulator with key performance parameters labeled. cs8126, -1, -2
5 lead 7 lead 16 lead thermal data to-220 d 2 pak soic wide r jc typ 2.1 2.1 23 c/w r ja typ 50 10-50* 105 c/w *depending on thermal properties of substrate. r ja = r jc + r ca . d lead count metric english max min max min 16 lead so wide 10.50 10.10 .413 .398 8 cs8126, -1, -2 package specification package thermal data package dimensions in mm (inches) surface mount wide body (dw); 300 mil wide 1.27 (.050) bsc 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) d 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) ref: jedec ms-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 2.35 (.093) 0.30 (.012) 0.10 (.004) 5 lead to-220 (t) straight 2.87 (.113) 2.62 (.103) 6.93(.273) 6.68(.263) 9.78 (.385) 10.54 (.415) 1.02(.040) 0.63(.025) 1.83(.072) 1.57(.062) 0.56 (.022) 0.36 (.014) 2.92 (.115) 2.29 (.090) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 6.55 (.258) 5.94 (.234) 14.22 (.560) 13.72 (.540) 1.02 (.040) 0.76 (.030) 3.71 (.146) 3.96 (.156) 14.99 (.590) 14.22 (.560) 5 lead to-220 (tha) horizontal 0.81(.032) 1.70 (.067) 6.81(.268) 1.40 (.055) 1.14 (.045) 5.84 (.230) 6.60 (.260) 6.83 (.269) 0.56 (.022) 0.36 (.014) 10.54 (.415) 9.78 (.385) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146) 1.68 (.066) typ 14.99 (.590) 14.22 (.560) 2.77 (.109) 2.29 (.090) 2.92 (.115) 4.83 (.190) 4.06 (.160) 2.87 (.113) 2.62 (.103) 5 lead to-220 (tva) vertical 1.68 (.066) typ 1.70 (.067) 7.51 (.296) 1.78 (.070) 4.34 (.171) 0.56 (.022) 0.36 (.014) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 14.99 (.590) 14.22 (.560) 2.92 (.115) 2.29 (.090) .94 (.037) .69 (.027) 8.64 (.340) 7.87 (.310) 6.80 (.268) 10.54 (.415) 9.78 (.385) 2.87 (.113) 2.62 (.103) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146)
9 part number description cs8126-1yt5 5 lead to-220 straight cs8126-1ytva5 5 lead to-220 vertical cs8126-1ytha5 5 lead to-220 horizontal cs8126-2gt5 5 lead to-220 straight cs8126-2gtva5 5 lead to-220 vertical CS8126-2GTHA5 5 lead to-220 horizontal cs8126-1ythe5 5 lead to-220 surface mount cs8126-1yther5 5 lead to-220 surface mount (tape & reel) cs8126ydps7 7 lead d 2 pak short-leaded cs8126ydpsr7 7 lead d2pak short-leaded (tape & reel) cs8126ydw16 16 lead soic wide cs8126ydwr16 16 lead soic wide (tape & reel) rev. 5/4/99 ordering information package specification: continued cs8126, -1, -2 package dimensions in mm (inches) 5 lead to-220 (the) smd 10.3 (.405) 10.0 (.395) 3.96 (.156) 3.71 (.146) 2.87 (.1 13) 2.61 (.103) 14.6 (.575) 8.40 (.331) .914 (.036) .711 (.028) 1.70 (.067) 6.80 (.268) 4.44 (.175) .254 (.010) .000 (.000) b .102 (.004) max a 1.40 (.055) 1.14 (.045) 5 (5 places) 14.0 (.550) 2.66 (.105) 2.56 (.101) 2.03 (.080) .254 (.010) ref notes: 1. dimensions exclusive of mold flash and metal burrs. 2. footpad length measured from lead tip with ref. to datum . 3. coplanarity .004 max. reference plane standoff height .000?010 . b a 7 lead d 2 pak (dps)* short-leaded 1.98 (.078) 1.47 (.058) 14.71 (.579) 13.69 (.539) 4.57 (.180) 4.31 (.170) 1.40 (.055) 1.14 (.045) 2.79 (.110) 2.54 (.100) terminal 8 7.75 (.305) ref 6.50 (.256) ref 10.31 (.406) 10.05 (.396) 1.27 (.050) ref 1.68 (.066) 1.40 (.055) .254 (.010) ref 0.91 (.036) 0.66 (.026) 8.53 (.336) 8.28 (.326) 0.10 (.004) 0.00 (.000) *on semiconductor short-leaded footprint on semiconductor and the on logo are trademarks of semiconductor components industries, llc (scillc). on semiconductor reserves the right to make changes without further notice to any products herein. for additional infor- mation and the latest available information, please contact your local on semiconductor representative. ? semiconductor components industries, llc, 2000
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